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oai:www.ideals.illinois.edu:2142/20676 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Rao, Vasant B. Yeh, David Ching-kai 2011-05-07T12:46:05Z 2011-05-07T12:46:05Z 10000-01-01 1990 Circuit simulation is an indispensable tool in the design and analysis of Very Large Scale Integrated (VLSI) circuits. The most widely used circuit simulators rely on direct methods and offer the most accurate, reliable, and technology-independent means of simulating integrated circuits. The simulation process is inherently very computation intensive and, hence, can require a significant portion of the computational resources available for the development of VLSI circuits. With the use of multiprocessor computers becoming more widespread, there exists an opportunity to speed up the simulation by partitioning the circuit so that the computation may be spread among the processors. To accomplish this, the circuit is partitioned into subcircuits using a node tearing method. If the circuit matrix is ordered subcircuit by subcircuit followed by the tearing nodes, then the matrix takes a bordered-block-diagonal form and the LU-factorization of the diagonal blocks may take place in parallel. This thesis defines the important objectives for this partitioning task and presents two algorithms that may be used to meet the partitioning goals. The first algorithm is an iterative improvement algorithm and the second is a network flow algorithm. Partitioning results and speedups are given for a variety of circuits. Made available in DSpace on 2011-05-07T12:46:05Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9026360.pdf: 4333545 bytes, checksum: 78de25b09f58f98cac81eb07dbb8a43e (MD5) Previous issue date: 1990 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:45:31Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:20:10-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9026360 (UMI)AAI9026360 http://hdl.handle.net/2142/20676 eng Copyright 1990 Yeh, David Ching-kai Engineering, Electronics and Electrical Partitioning algorithms for parallel circuit simulation text Engineering, Electronics and Electrical Engineering, Electronics and Electrical University of Illinois at Urbana-Champaign Dissertation Ph.D.