2026-09-20T22:29:06Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/20795 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Patel, Janak H. Kunda, Ramachandra P. 2011-05-07T12:49:31Z 2011-05-07T12:49:31Z 10000-01-01 1990 Test generation is an important part of a circuit as the test vectors are used during the design, manufacture, system integration, and throughout the life-cycle of the circuit in order to detect the presence of defects. The very large scale integration (VLSI) test generation problem has been one of the most complex and time-consuming problems. This is a major bottleneck in the design cycle of the circuit. The problem is further complicated by rapid advances in VLSI technology, such as in CMOS, where the traditional stuck-at fault model is inadequate, and the increase in gate to pin ratio makes it difficult to access and observe the internal signals. In this thesis, we present two different approaches to attack this problem. The first approach is concerned mainly with the generation of functional-level tests that are used during system debug and integration. A functional diagnostic methodology as well as techniques to diagnose various blocks of a multiprocessor system are presented. The approach has been used successfully to debug and integrate a prototype multiprocessor system. In the second approach, we present a hierarchical and high-level model which uses architectural-level primitives for fault propagation and signal value justification to speed up the automatic test vector generation process. We present methods for fault propagation and value justification through the architectural-level primitives. In order to reduce the number of backtracks, the algorithm employs the strategy of dependency-directed backtracking, which attempts to resolve the conflicts by changing the signal values causing the conflict. Experimental results using this approach for test vector generation are presented. Made available in DSpace on 2011-05-07T12:49:31Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9114304.pdf: 4218521 bytes, checksum: 14374e6063da3e41f03dd787886bfa87 (MD5) Previous issue date: 1990 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:46:19Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:20:43-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9114304 (UMI)AAI9114304 http://hdl.handle.net/2142/20795 eng Copyright 1990 Kunda, Ramachandra P. Engineering, Electronics and Electrical Use of architectural-level primitives in system-level diagnosis and speed up of test vector generation text Electrical and Computer Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.