2026-09-19T12:45:49Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/20822 2023-07-10 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

text Liu, C.L. Sun, Yachyang 2011-05-07T12:50:19Z 2011-05-07T12:50:19Z 10000-01-01 1994 Various physical design problems in Very Large Scale Integrated (VLSI) circuits and Field-Programmable Gate Arrays (FPGA) are studied in this thesis. Specifically, we study (1) the area minimization problem in floorplans with L-shaped modules; (2) the channel routing problem in the single layer customization technology; (3) the area routing problem in the channelless single layer customization technology; (4) the design of new routing architectures and algorithms for FPGAs; (5) the congestion-balanced approach for the FPGA placement problem. Made available in DSpace on 2011-05-07T12:50:19Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9512566.pdf: 6700240 bytes, checksum: 19af65ed806b6fc44b5bddfd797b9179 (MD5) Previous issue date: 1994 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:46:32Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:20:52-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9512566 (UMI)AAI9512566 http://hdl.handle.net/2142/20822 eng Copyright 1994 Sun, Yachyang Mathematics Engineering, Electronics and Electrical Computer Science Algorithmic results on physical design problems in VLSI and FPGA Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.