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oai:www.ideals.illinois.edu:2142/21265 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Patel, Janak H. Cheong, Hoichi 2011-05-07T13:03:30Z 2011-05-07T13:03:30Z 10000-01-01 1990 The cache coherence maintenance problem has been the major obstacle in using private cache memory to reduce memory access latency in large-scale multiprocessor systems. Two compiler-directed solutions, the fast selective invalidation scheme and the version control scheme, are proposed in this work. Contrary to the existing hardware-based approach, the proposed schemes expose caches to software-directed management techniques which have the advantage of requiring no global communication and maintaining expandability of the multiprocessor systems. The fast selective scheme employs compile-time flow analysis techniques to detect cache data that contain obsolete values, and uses simple hardware to prevent using such data. The version control scheme defines the concept of version of a program variable to maintain up-to-date copies in the cache and solves the difficult problem of preserving temporal locality in parallel execution. Unlike existing software-directed schemes, both schemes achieve selective invalidation with very low time penalty. The version control scheme is also extended to hierarchical cache systems for which no satisfactory solutions exist. Detailed discussion on the development of these schemes and their proofs are presented. Finally, experimental data by simulation are shown to support the advantage of the schemes. Made available in DSpace on 2011-05-07T13:03:30Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9021663.pdf: 6284159 bytes, checksum: 4ad762ab6e2da6b0650b016f4d121b92 (MD5) Previous issue date: 1990 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:49:36Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:22:35-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9021663 (UMI)AAI9021663 http://hdl.handle.net/2142/21265 eng Copyright 1990 Cheong, Hoichi Engineering, Electronics and Electrical Computer Science Compiler-directed cache coherence strategies for large-scale shared-memory multiprocessor systems text Electrical and Computer Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.