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oai:www.ideals.illinois.edu:2142/21540 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

http://hdl.handle.net/2142/21540 eng Copyright 1990 Roy, Kaushik Engineering, Electronics and Electrical Computer Science Timing verification and synthesis of circuits for delay fault testability text Patel, Janak H. Roy, Kaushik 2011-05-07T13:11:39Z 2011-05-07T13:11:39Z 10000-01-01 1990 This thesis concerns the problem of timing verification and synthesis of circuits for robust delay fault testability. The timing verification algorithm uses Register Transfer Level (RTL) descriptions to eliminate false paths (non-sensitizable) due to redundancy, reconvergent fanout, and control signal constraints. The RTL descriptions help to prune the search space because only valid paths are considered. The critical paths obtained from the timing verifier have to be tested for any delay faults. To make the robust delay test generation easier, multilevel combinational logic circuits are synthesized for delay fault testability. Given a multilevel description of a combinational logic circuit, blocked or dependent paths may be present. Blocked or dependent paths due to reconvergent fanout can destroy robustness of tests. A set of path segments called essential paths is checked for blockage or dependency, and a local transformation enhances the delay fault testability of the circuit. It has been shown that a robust delay test can be obtained as a by-product of the logic synthesis procedure. Made available in DSpace on 2011-05-07T13:11:39Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9114393.pdf: 3973884 bytes, checksum: 99a17f11b8ffdb66b5496af370c6af19 (MD5) Previous issue date: 1990 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:51:29Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:23:38-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9114393 (UMI)AAI9114393 Electrical and Computer Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.