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oai:www.ideals.illinois.edu:2142/21610 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Hajj, Ibrahim N. Najm, Farid Nasri 2011-05-07T13:13:48Z 2011-05-07T13:13:48Z 10000-01-01 1989 This thesis presents a new technique for simulating integrated circuits, called probabilistic simulation. Using this technique, statistical descriptions of the voltage waveforms at the circuit primary inputs are used to derive corresponding statistical descriptions of the internal voltages and currents. To illustrate its utility, we use this approach to analyze integrated circuit reliability. Specifically, we focus on the problem of predicting the susceptibility of a given design to electromigration failures. We show that the median time-to-failure (MTF), due to electromigration, can be related to a stochastic model of the power supply and ground currents. Most of the thesis is then devoted to explaining the probabilistic simulation technique, adapted to CMOS VLSI digital circuits, and how it can be used to derive the required statistical descriptions of the current. This approach has been implemented in the program CREST, and has shown excellent accuracy and dramatic speedups compared to traditional approaches. We describe the probabilistic simulation technique and its implementation, and present the results of CREST runs on a variety of circuits. Made available in DSpace on 2011-05-07T13:13:48Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9010965.pdf: 3698333 bytes, checksum: 8ae430d3823b83c5c4130a89617114a7 (MD5) Previous issue date: 1989 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:52:00Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:23:54-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9010965 (UMI)AAI9010965 http://hdl.handle.net/2142/21610 eng Copyright 1989 Najm, Farid Nasri Engineering, Electronics and Electrical Probabilistic simulation for reliability analysis of VLSI circuits text Electrical and Computer Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.