2026-09-20T13:54:30Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/21879 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Patel, Janak H. Levitt, Marc Elliot 2011-05-07T13:21:58Z 2011-05-07T13:21:58Z 10000-01-01 1990 The world is a more competitive place than before, and time is a key component in any winning competitive strategy. This thesis provides methods by which companies can become more efficient time-based competitors in the semiconductor and computer businesses. Methods are presented in two very important areas, design and manufacture. In the design area, the issues of test and design-for-test are examined since they are important and growing parts of the total design cycle. A productivity study is presented and, from the insight gained, models are developed to accurately predict important issues in test and design-for-test. The productivity models are then combined with economic models to achieve a complete life cycle picture of the integrated circuit that not only includes die economics but also time-to-market effects and quality issues. Examples are presented to demonstrate the use of the models. In the manufacturing end of the semiconductor business, a method is developed that allows just-in-time techniques to be applied to fabrication areas. The technique consists of unraveling the job shop by concentrating on the bottleneck and/or critical workstations and then calculating the number of Kanban cards needed to control inventory and production. An extensive simulation-based evaluation of the method is presented, comparing it to many other techniques for three types of fabrication areas. These are: single bottleneck with no hot-lots, multiple bottlenecks with no hot-lots, and single bottleneck with hot-lots. In all cases the just-in-time method developed performs best overall. Made available in DSpace on 2011-05-07T13:21:58Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9114314.pdf: 3943464 bytes, checksum: d6eb578afca1690e2053fe4e21ef721d (MD5) Previous issue date: 1990 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:53:49Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:24:56-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9114314 (UMI)AAI9114314 http://hdl.handle.net/2142/21879 eng Copyright 1990 Levitt, Marc Elliot Engineering, Electronics and Electrical Operations Research Time-based strategies for semiconductor manufacture and test text Electrical and Computer Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.