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Patel, Janak H. Niermann, Thomas Michael 2011-05-07T13:31:58Z 2011-05-07T13:31:58Z 10000-01-01 1991 Test pattern generation has progressed to a stage at which automatic test generation gives satisfactory fault coverage on almost any combinational circuit. However, the same is not true of sequential circuit test generation. While scan-based approaches can convert the sequential circuit into a combinational circuit for testing purposes, the cost of a complete scan design methodology can be prohibitive in both area overhead and performance degradation. Therefore, an efficient sequential circuit test generation system which generates tests for all detectable faults and identifies all untestable faults in the original design is necessary. The information on untestable faults could be used to add minimal design for test hardware to make these faults testable. This thesis presents several new techniques to improve the performance of sequential circuit test generators. Among the concepts presented are unnecessary state elimination, and the use of fault simulation knowledge to increase test coverage during a second phase of test generation, a targeted D element technique for D propagation, and the use of the good circuit state knowledge. The concepts presented in the thesis were implemented and tested on the ISCAS sequential benchmark circuits. This thesis presents an improved fault simulation algorithm based on a combination of the parallel, concurrent and differential fault simulation algorithms. This fault simulator is shown to require much less memory while being 6 to 67 times faster than a traditional concurrent fault simulator. Made available in DSpace on 2011-05-07T13:31:58Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9136684.pdf: 4141771 bytes, checksum: cf24e02ecaababfd82864d89e2a52775 (MD5) Previous issue date: 1991 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:55:57Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:26:07-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9136684 (UMI)AAI9136684 http://hdl.handle.net/2142/22192 eng Copyright 1991 Niermann, Thomas Michael Engineering, Electronics and Electrical Techniques for sequential circuit automatic test generation text Electrical and Computer Engineering Electrical and Computer Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.