2026-09-19T05:22:36Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/22282 2023-07-10 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

Muroga, Saburo Chen, Kuang-Chien 2011-05-07T13:34:55Z 2011-05-07T13:34:55Z 10000-01-01 1991 As VLSI integration size and chip complexity keep increasing, logic design is becoming more complex and it must be automated. The increasing demand for ASIC (Application Specific Integrated Circuits) also needs design efficiency and cost effectiveness which can only be achieved by effective automatic logic synthesis tools. In this thesis, two important network realization means, PLA's and multi-level networks (i.e., random logic networks), are studied, and effective algorithms are developed for the use as automatic logic synthesis tools. For the design based on PLA's, an absolute PLA minimization algorithm, PMIN, is presented. PMIN can handle a much larger range of functions than previous absolute minimization algorithms because it incorporated new algorithms for prime implicant generation and the extraction of a minimal subset of prime implicants. Also, a heuristic input variable assignment algorithm for the design of decoded-PLA's using multi-input decoders is incorporated in PMIN, and experimental results show that significant saving in area can be achieved for many functions. For the design of multi-level networks, a synthesis and optimization algorithm, SYLON-DREAM, is presented, which includes algorithms for network design, area optimization and timing optimization. Extensive experimental results are shown to demonstrate the capabilities of these algorithms. Made available in DSpace on 2011-05-07T13:34:55Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9124394.pdf: 11224308 bytes, checksum: df242623f6dbd930a72bc5844c86f83d (MD5) Previous issue date: 1991 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:56:34Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:26:27-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9124394 (UMI)AAI9124394 http://hdl.handle.net/2142/22282 eng Copyright 1991 Chen, Kuang-Chien Engineering, Electronics and Electrical Computer Science Logic synthesis and optimization algorithms text Engineering, Electronics and Electrical Computer Science Computer Science Dissertation Ph.D.