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oai:www.ideals.illinois.edu:2142/22440 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Saab, Daniel G. Chen, Chung-Hsing 2011-05-07T13:39:54Z 2011-05-07T13:39:54Z 10000-01-01 1993 In this thesis, a behavioral-level testability analysis approach is presented. This approach is based on analyzing the circuit behavioral description (similar to a C program) to estimate its testability by identifying controllable and observable circuit nodes. This information can be used by a test generator to gain better access to internal circuit nodes and to reduce its search space. The results of the testability analyzer can also be used to select test points or partial scan flip-flops in the early design phase. Based on selection criteria, a novel Synthesis for Testability approach called Test Statement Insertion (TSI) is proposed, which modifies the circuit behavioral description directly. Test Statement Insertion can also be used to modify circuit structural description to improve its testability. As a result, Synthesis for Testability methodology can be combined with an existing behavioral synthesis tool to produce more testable circuits. Made available in DSpace on 2011-05-07T13:39:54Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9314851.pdf: 3502144 bytes, checksum: 3faacc92ad8aedeac667e7d491671365 (MD5) Previous issue date: 1993 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:57:38Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:27:02-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9314851 (UMI)AAI9314851 http://hdl.handle.net/2142/22440 eng Copyright 1993 Chen, Chung-Hsing Engineering, Electronics and Electrical BETA: Behavioral Testability Analyzer and its applications to high-level test generation and synthesis for testability text Engineering, Electronics and Electrical Engineering, Electronics and Electrical University of Illinois at Urbana-Champaign Dissertation Ph.D.