2026-09-18T20:52:17Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/22891 2023-07-10 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

eng Copyright 1996 Park, Chaeryung Computer Science Liu, C.L. Park, Chaeryung 2011-05-07T13:54:56Z 2011-05-07T13:54:56Z 10000-01-01 1996 High-level synthesis becomes increasingly important in the area of VLSI CAD. This thesis addresses scheduling and allocation in high-level synthesis. Specifically, we study the problem of register allocation in the presence of conditional blocks, such as if and case blocks and loops in the data flow graph. A conditional block in a data flow graph introduces the opportunity of conditional resource sharing among the values of variables in the mutually exclusive conditional branches of the conditional block. We also consider the problem of scheduling, allocation and memory module partition to reduce power consumption. We offer an integrated high-level synthesis sytem SAMP to the solution of the scheduling, allocation (memory units and functional units), functional module selection and partitioning for low power design. SAMP exploits two possibilities of reducing total power consumption. First, it provides a general library in which there are functional modules that perform the same computation but have different speeds and power consumption. Often, low power functional modules are slower while high power functional modules are faster. Second it allows dynamic localized shutdown of functional modules by clock gating to reduce power consumption. Since CMOS circuits consume only a negligible amount of power when they are not switching, inhibiting unnecessary circuit switching activities in functional modules and clock signals will lead to a reduction of power consumption. Made available in DSpace on 2011-05-07T13:54:56Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9625178.pdf: 3314576 bytes, checksum: 1dfd3c304d63f6c0d29887b346dc1821 (MD5) Previous issue date: 1996 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:00:44Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:28:45-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9625178 (UMI)AAI9625178 http://hdl.handle.net/2142/22891 Task scheduling in high-level synthesis text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.