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        <identifier>oai:www.ideals.illinois.edu:2142/22966</identifier>
        <datestamp>2023-07-10</datestamp>
        <setSpec>col_2142_5131</setSpec>
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        <thesis xmlns="http://www.ndltd.org/standards/metadata/etdms/1.1/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:dc="http://purl.org/dc/elements/1.1/" xsi:schemaLocation="http://www.ndltd.org/standards/metadata/etdms/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdms11.xsd http://purl.org/dc/elements/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdmsdc.xsd">
          <dc:contributor>Hajj, Ibrahim N.</dc:contributor>
          <dc:creator>Chung, Pi-Yu</dc:creator>
          <dc:date>2011-05-07T13:57:29Z</dc:date>
          <dc:date>2011-05-07T13:57:29Z</dc:date>
          <dc:date>10000-01-01</dc:date>
          <dc:date>1994</dc:date>
          <dc:description>A CAD tool ACCORD has been developed for design verification and design error correction. ACCORD verifies a gate-level implementation of a design in terms of its functional description. If the functionality of an implementation is incorrect, the tool identifies the error locations and makes corrections automatically.</dc:description>
          <dc:description>Our approach is based on the simple design error model proposed by Abadir et al. (1). The model includes eight commonly encountered design errors: simple gate replacement, a missing/extra inverter, a missing/extra gate, a missing/extra gate input and an incorrectly placed gate input. The experiment described in (2) showed that the simple design error model covers 98% of the errors made by designers.</dc:description>
          <dc:description>The main contributions of this thesis are (1) developing an efficient and exact search algorithm for single design error; (2) proposing fast gate correction and line correction procedures; and (3) extending the search and correction methods to rectify multiple design errors.</dc:description>
          <dc:description>Experimental results on ISCAS and MCNC benchmark circuits show that 100% of single design errors, 68% of two design errors and 54% of three design errors can be corrected by our tool within an hour of CPU time.</dc:description>
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license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5)
9416349.pdf: 4021590 bytes, checksum: 496822eb556448103c75e5fca2c6b867 (MD5)
  Previous issue date: 1994</dc:description>
          <dc:description>Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:01:15Z
Item is restricted indefinitely.</dc:description>
          <dc:description>Restriction data tranferred 2014-07-01T11:29:03-05:00
Original Data
Group with Access UIUC Users [automated]
Release Date: none
Reason: ETDs are only available to UIUC Users without author permission</dc:description>
          <dc:description>ETDs are only available to UIUC Users without author permission</dc:description>
          <dc:description>U of I Only</dc:description>
          <dc:identifier>AAI9416349</dc:identifier>
          <dc:identifier>(UMI)AAI9416349</dc:identifier>
          <dc:identifier>http://hdl.handle.net/2142/22966</dc:identifier>
          <dc:language>eng</dc:language>
          <dc:rights>Copyright 1994 Chung, Pi-Yu</dc:rights>
          <dc:subject>Engineering, Electronics and Electrical</dc:subject>
          <dc:subject>Computer Science</dc:subject>
          <dc:title>Diagnosis and correction of logic design errors</dc:title>
          <dc:type>text</dc:type>
          <degree>
            <department>Engineering, Electronics and Electrical</department>
            <department>Computer Science</department>
            <discipline>Engineering, Electronics and Electrical</discipline>
            <discipline>Computer Science</discipline>
            <grantor>University of Illinois at Urbana-Champaign</grantor>
            <level>Dissertation</level>
            <name>Ph.D.</name>
          </degree>
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