2026-09-19T04:44:14Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/22981 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Banerjee, Prithviraj Patil, Srinivas 2011-05-07T13:57:57Z 2011-05-07T13:57:57Z 10000-01-01 1991 With increase in complexity of digital circuits, it has become extremely important to detect faults to ensure correct operation of a digital circuit. Since test generation and fault simulation for circuits of VLSI complexity can take a prohibitive amount of time, speeding up test generation and fault simulation algorithms by either using better uniprocessor heuristics or by using the tremendous computing power available on multiprocessors thus becomes important. The design and analysis of parallel algorithms for test generation and fault simulation are the focus of this thesis research. We first categorize various parallel processing techniques available for test generation and fault simulation. We then propose a parallel search method to overcome the deficiencies of inaccurate search heuristics. We show that this method not only results in faster execution of the test generation algorithm but also results in a better quality of the solution. We also propose a performance model to evaluate the parallel search technique. We then propose fault partitioning techniques to speed up test generation for faults which are relatively easy to detect. The objective of the fault partitioning techniques is to maximize concurrency without affecting the quality of the overall solution. We propose load balancing techniques which try to minimize the processor idle time with very low communication overhead. We propose a performance model which takes into account the various trade-offs in exploiting parallelism in a test generation/fault simulation environment. Finally, we present a parallel test generation system for sequential circuits. A parallel search technique is used to accelerate test generation for hard to detect faults, and a circuit partitioned approach is used to accelerate fault simulation. Made available in DSpace on 2011-05-07T13:57:57Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9124467.pdf: 5751613 bytes, checksum: aaf96417e7558989f9c47080fdf0db4c (MD5) Previous issue date: 1991 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:01:21Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:29:06-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9124467 (UMI)AAI9124467 http://hdl.handle.net/2142/22981 eng Copyright 1991 Patil, Srinivas Engineering, Electronics and Electrical Parallel algorithms for test generation and fault simulation text Engineering, Electronics and Electrical Engineering, Electronics and Electrical University of Illinois at Urbana-Champaign Dissertation Ph.D.