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oai:www.ideals.illinois.edu:2142/23126 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Chang, Mi-Chang 2011-05-07T14:03:05Z 2011-05-07T14:03:05Z 10000-01-01 1989 The direct-method circuit simulation technique solves the entire system at every iteration and thus avoids the problem of slow convergence or even nonconvergence, which could occur when relaxation-based techniques are applied. However, the parallelism of the direct method is not as obvious as that of the relaxation technique. The parallelism in the LU factorization without tearing has been found to be small and one level node tearing could have a large border size if it is forced to partition the circuit into a fixed number of subcircuits. In this thesis we increase the parallelism by using a multilevel node tearing method which maintains a minimum border size while trying to balance the subcircuit sizes. The problems of how to maximize the speedup by scheduling the subcircuits correctly and by choosing the optimal number of levels of partitioning are also studied. A parallel circuit simulator, iPRIDE, is implemented on an ALLIANT FX/8 computer using these techniques. A speedup of 7.3 using 8 processors has been achieved. Made available in DSpace on 2011-05-07T14:03:05Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 8916223.pdf: 7308068 bytes, checksum: 79426a62abd4528fc7669b6a0ca79cd9 (MD5) Previous issue date: 1989 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:02:21Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:29:38-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI8916223 (UMI)AAI8916223 http://hdl.handle.net/2142/23126 eng Copyright 1989 Chang, Mi-Chang Engineering, Electronics and Electrical Computer Science Efficient direct-method parallel circuit simulation using multilevel node tearing text Electrical and Computer Engineering Electrical and Computer Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.