2026-09-21T19:47:44Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/23569 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Restriction data tranferred 2014-07-01T11:31:18-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9624306 (UMI)AAI9624306 http://hdl.handle.net/2142/23569 eng Copyright 1995 Chang, Edward Chongyul Engineering, Electronics and Electrical Full and approximate modeling of transmission lines for high-speed interconnect simulation text Kang, Sung Mo Chang, Edward Chongyul 2011-05-07T14:19:02Z 2011-05-07T14:19:02Z 10000-01-01 1995 This thesis addresses modeling and simulation of high speed interconnects. Both a full transmission line model for accuracy and an approximate model for simulation efficiency are presented. Also techniques to improve simulation efficiency are explained. The performance of high speed digital integrated circuits with finer feature sizes is limited by the interconnection delay rather than by the device switching time. Transmission line effects such as reflection, dispersion, attenuation and crosstalk can cause false signals, which, in turn, can cause malfunction of the system. Thus accurate modeling and transient simulation of lossy transmission lines have become essential in reliable high speed digital circuit design. In this thesis, models for both single and coupled transmission lines are developed. Several synthesis techniques to find equivalent circuit models are addressed, including optimization and curve fitting techniques. Since the transient simulation of the lossy transmission lines requires a convolution integral, which becomes quadratically expensive as the simulated time interval increases, techniques to improve its efficiency from quadratic to linear will be presented. Even though the transmission line model provides the best accuracy, due to its high computational cost, a simpler and faster yet accurate model and a simulation tool are needed to evaluate the timing of high speed digital circuits. Thus, a simplified circuit model based on a combination of Taylor series expansion and Pade synthesis is developed in this thesis. Also iTISET (iLLINOIS Tree Interconnect Structure Evaluation Tool) has been implemented as a stand-alone tool to evaluate an interconnect tree quickly yet accurately. Made available in DSpace on 2011-05-07T14:19:02Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9624306.pdf: 3513904 bytes, checksum: 15c85c646523b7de21e26aafb04b9af4 (MD5) Previous issue date: 1995 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:05:21Z Item is restricted indefinitely. Engineering, Electronics and Electrical Engineering, Electronics and Electrical University of Illinois at Urbana-Champaign Dissertation Ph.D.