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        <identifier>oai:www.ideals.illinois.edu:2142/23634</identifier>
        <datestamp>2023-07-10</datestamp>
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        <thesis xmlns="http://www.ndltd.org/standards/metadata/etdms/1.1/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:dc="http://purl.org/dc/elements/1.1/" xsi:schemaLocation="http://www.ndltd.org/standards/metadata/etdms/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdms11.xsd http://purl.org/dc/elements/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdmsdc.xsd">
          <dc:contributor>Banerjee, Prithviraj</dc:contributor>
          <dc:creator>Kling, Ralph Michael</dc:creator>
          <dc:date>2011-05-07T14:21:23Z</dc:date>
          <dc:date>2011-05-07T14:21:23Z</dc:date>
          <dc:date>10000-01-01</dc:date>
          <dc:date>1990</dc:date>
          <dc:description>We introduce the new optimization method of Simulated Evolution (SE), which is designed to find near optimal solutions to problems which are hard to solve by standard methods. The new algorithm is discussed in detail and a variety of measurements are taken to evaluate its performance under various conditions. In addition, a theoretical framework is introduced to formally describe the algorithm. A Markov analysis is performed using this mathematical model to analyze convergence properties.</dc:description>
          <dc:description>The Standard Cell placement problem in the VLSI design area was chosen as a representative problem for applying SE techniques. A new hierarchical placement technique using windowing methods is introduced. A complete placement program has been developed and thoroughly tested on a variety of industrial benchmark circuits. A comparative performance analysis with the most successful Simulated Annealing-based placement program is presented.</dc:description>
          <dc:description>The SE algorithm has been implemented on several different sequential and parallel computing platforms. An evaluation of the achievable parallelism has been performed in each case. Furthermore, a special purpose coprocessor which speeds up wire length calculations as needed by placement programs has been designed, fabricated and tested.</dc:description>
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  Previous issue date: 1990</dc:description>
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Item is restricted indefinitely.</dc:description>
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Original Data
Group with Access UIUC Users [automated]
Release Date: none
Reason: ETDs are only available to UIUC Users without author permission</dc:description>
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          <dc:description>U of I Only</dc:description>
          <dc:identifier>AAI9114300</dc:identifier>
          <dc:identifier>(UMI)AAI9114300</dc:identifier>
          <dc:identifier>http://hdl.handle.net/2142/23634</dc:identifier>
          <dc:language>eng</dc:language>
          <dc:rights>Copyright 1990 Kling, Ralph Michael</dc:rights>
          <dc:subject>Engineering, Electronics and Electrical</dc:subject>
          <dc:title>Optimization by simulated evolution and its application to cell placement</dc:title>
          <dc:type>text</dc:type>
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            <department>Engineering, Electronics and Electrical</department>
            <discipline>Engineering, Electronics and Electrical</discipline>
            <grantor>University of Illinois at Urbana-Champaign</grantor>
            <level>Dissertation</level>
            <name>Ph.D.</name>
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