2026-09-21T17:38:40Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/24101 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Rosenbaum, Elyse Rosenbaum, Elyse Feng, Milton Shanbhag, Naresh R. Schutt-Ainé, José E. Olson, Nicholas A. 2011-05-25T14:50:54Z 2011-05-25T14:50:54Z 2011-05-25T14:50:54Z 2011-05 Advances in integrated circuit design and packaging techniques have introduced new ESD-susceptible (Electrostatic Discharge) circuit interfaces. This document will introduce these interfaces and the methods that were used to investigate their ESD robustness. Two test chips were designed to aid the analysis. The specialized design choices that allow for distinguishing between multiple failure locations are thoroughly illustrated. The testing plan is detailed and the test chip measurement results are analyzed. The results will compare different ESD protection techniques and illustrate the importance of having ESD protection at these interfaces. The results will also show how some interfaces are inherently more robust than others during a CDM (Charged Device Model) event. Finally, the effects on the intensity of the CDM stress based on single-die or stacked-die packages will be compared. Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2011-04-19T14:11:58Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Olson_Nicholas.docx: 2338306 bytes, checksum: 8feda660a20833a09a08d30e4cdc2a9c (MD5) Olson_Nicholas.pdf: 1227094 bytes, checksum: b018bc91f49ad7fe9eb5e677de5f8fc9 (MD5) Made available in DSpace on 2011-05-25T14:50:54Z (GMT). No. of bitstreams: 3 Olson_Nicholas.pdf: 1227094 bytes, checksum: b018bc91f49ad7fe9eb5e677de5f8fc9 (MD5) license.txt: 4063 bytes, checksum: e7908f494bd72fc1a40b16dab3ecd378 (MD5) Olson_Nicholas.docx: 2338306 bytes, checksum: 8feda660a20833a09a08d30e4cdc2a9c (MD5) http://hdl.handle.net/2142/24101 en Copyright 2011 Nicholas A. Olson Charged Device Model Charged Device Model (CDM) Electrostatic Discharge (ESD) Electrostatic Discharge System on a Chip System in a Package Charged device model electrostatic discharge failures in system on a chip and system in a package designs Electrical & Computer Eng 1933 Electrical & Computer Engr 1200 University of Illinois at Urbana-Champaign Dissertation Ph.D. PHD:Electr & Computer Eng-UIUC 10KS1200PHD