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        <identifier>oai:www.ideals.illinois.edu:2142/24241</identifier>
        <datestamp>2023-07-10</datestamp>
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        <thesis xmlns="http://www.ndltd.org/standards/metadata/etdms/1.1/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:dc="http://purl.org/dc/elements/1.1/" xsi:schemaLocation="http://www.ndltd.org/standards/metadata/etdms/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdms11.xsd http://purl.org/dc/elements/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdmsdc.xsd">
          <dc:contributor>Kumar, Rakesh</dc:contributor>
          <dc:creator>Kesler, David R.</dc:creator>
          <dc:date>2011-05-25T15:01:29Z</dc:date>
          <dc:date>2011-05-25T15:01:29Z</dc:date>
          <dc:date>2011-05-25T15:01:29Z</dc:date>
          <dc:date>2011-05</dc:date>
          <dc:description>Gradient descent, conjugate gradient, and other iterative algorithms are a
powerful class of algorithms; however, they can take a long time for conver-
gence. Baseline accelerator designs feature insu cient coverage of operations
and do not work well on the problems we target. In this thesis we present
a novel hardware architecture for accelerating gradient descent and other
similar algorithms. To support this architecture, we also present a sparse
matrix-vector storage format, and software support for utilizing the format,
so that it can be e ciently mapped onto hardware which is also well suited for
dense operations. We show that the accelerator design outperforms similar
designs which target only the most dominant operation of a given algorithm,
providing substantial energy and performance bene ts. We further show that
the accelerator can be reasonably implemented on a general purpose CPU
with small area overhead.</dc:description>
          <dc:description>Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2011-03-28T13:39:41Z
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University of Illinois Theses &amp; Dissertations (ID: 1)
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          <dc:identifier>http://hdl.handle.net/2142/24241</dc:identifier>
          <dc:language>en</dc:language>
          <dc:rights>Copyright 2011 David R. Kesler</dc:rights>
          <dc:subject>Gradient Descent</dc:subject>
          <dc:subject>Conjugate Gradient</dc:subject>
          <dc:subject>Hardware Acceleration</dc:subject>
          <dc:subject>Matrix Multiplication</dc:subject>
          <dc:title>A hardware acceleration technique for gradient descent and conjugate gradient</dc:title>
          <degree>
            <department>Electrical &amp; Computer Eng</department>
            <departmentCode>1933</departmentCode>
            <discipline>Electrical &amp; Computer Engr</discipline>
            <disciplineCode>1200</disciplineCode>
            <grantor>University of Illinois at Urbana-Champaign</grantor>
            <level>Thesis</level>
            <name>M.S.</name>
            <program>MS:Electr &amp; Computer Eng-UIUC</program>
            <programCode>10KS1200MS</programCode>
          </degree>
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