2026-09-20T10:50:23Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/24258 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Patel, Sanjay J. Venshtain, Simion 2011-05-25T14:51:03Z 2011-05-25T14:51:03Z 2011-05-25T14:51:03Z 2011-05 Memory model design is a major part of any modern processor architecture. There are many design choices and tradeoffs to be considered, and these often need to be tightly coupled to the processing unit's arcitecure. The increased popularity of massively parallel architectures has motivated researchers to further examine the memory model tradeoffs these types of architectures and their target applications present. This thesis will focus on Rigel, a 1024-core, general purpose massively parallel architecure. I will study the memory model design tradeoffs of the Rigel cluster, a subblock of the Rigel architecure, and attempt to propose a design configuration that is suitable to the unique requirements of the Rigel architecture. Rigel is an agressive design target and requires us to focus on the area and power impact of the memory model design choices. As a result, to study the design tradeoffs, I use an approach that utlizes an RTL implementation, combined with a custom design exploration flow built on top of production quality CAD tools. This flow allows us to extract accurate power and area results for each design point and pick points that provide us with the highest perfomance density. Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2011-02-22T14:58:58Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Venshtain_Simion.pdf: 3570032 bytes, checksum: ef56e9cf11af7e0899d0f5bf249210ce (MD5) Made available in DSpace on 2011-05-25T14:51:03Z (GMT). No. of bitstreams: 2 Venshtain_Simion.pdf: 3570032 bytes, checksum: ef56e9cf11af7e0899d0f5bf249210ce (MD5) license.txt: 4066 bytes, checksum: 5a30dc99b5fd114e80840409f3239d7f (MD5) http://hdl.handle.net/2142/24258 en Copyright 2011 Simion Venshtain Cache Interconnect Cache design Cache hierarchy Nonblocking cache RTL design exploration register transfer level (RTL) Rigel Massively parallel Accelerator Cache design exploration in a general purpose massively parallel architecture Electrical & Computer Eng 1933 Electrical & Computer Engr 1200 University of Illinois at Urbana-Champaign Thesis M.S. MS:Electr & Computer Eng-UIUC 10KS1200MS