2026-09-20T13:42:42Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/24396 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Patel, Sanjay J. Johnson, Daniel R. 2011-05-25T14:38:59Z 2011-05-25T14:38:59Z 2013-05-26T10:00:24Z 2011-05-25T14:38:59Z 2011-05 In this thesis, I describe the evaluation framework for Rigel, a 1024-core single-chip accelerator architecture designed for high throughput on visual computing and scientific workloads. I present an integrated evaluation framework for investigating co-designed architecture, compilers, programming models, and RTL implementation for massively parallel chip multiprocessors (CMPs). The research objective of the Rigel project, designing a prototype thousand-core chip, led to the development of the framework presented in this thesis. I describe the tools and techniques which enabled this work. The goal of this thesis is not to evaluate specific design tradeoffs, but to describe the tools we have developed for making these decisions. I motivate and describe our integrated performance simulator, code generator, and RTL implementation for evaluation of a novel 1024-core accelerator architecture. I demonstrate the utility of a flexible hardware-software interface supporting an evolving ISA for architectural design space exploration. Although I present experiences related to a particular design, the methods applied and lessons learned are more broadly applicable. I summarize some of the published work which this framework has enabled. Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2011-04-07T18:29:24Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 johnson_daniel.pdf: 5188421 bytes, checksum: 6eba3bd4e13ae3c96316c7a36621481b (MD5) Made available in DSpace on 2011-05-25T14:38:59Z (GMT). No. of bitstreams: 2 johnson_daniel.pdf: 5188421 bytes, checksum: 6eba3bd4e13ae3c96316c7a36621481b (MD5) license.txt: 4064 bytes, checksum: a74246056ea2c509c2c9c379fa0cfd9e (MD5) Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by William Ingram (wingram2@illinois.edu) on 2011-05-25T14:41:51Z Item is restricted until 2013-05-25T14:41:28Z Item reinstated by Sarah Shreeves (sshreeve@illinois.edu) on 2013-05-26T10:00:24Z Item was in collections: University of Illinois Dissertations and Theses (ID: 204) Dissertations and Theses - Electrical and Computer Engineering (ID: 446) No. of bitstreams: 3 johnson_daniel.pdf.txt: 125645 bytes, checksum: 87ccedca3edd55b11ea7d75e6e6773f8 (MD5) johnson_daniel.pdf: 5188421 bytes, checksum: 6eba3bd4e13ae3c96316c7a36621481b (MD5) license.txt: 4064 bytes, checksum: a74246056ea2c509c2c9c379fa0cfd9e (MD5) Item released from any restrictions by Sarah Shreeves (sshreeve@illinois.edu) on 2013-05-26T10:00:24Z http://hdl.handle.net/2142/24396 en Copyright 2011 Daniel R. Johnson Accelerator Chip Mulitprocessor Parallel Processing An evaluation framework for massively parallel accelerator processors Electrical & Computer Eng 1933 Electrical & Computer Engr 1200 University of Illinois at Urbana-Champaign Thesis M.S. PHD:Electr & Computer Eng-UIUC 10KS1200PHD