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Vasudevan, Shobha Athavale, Viraj 2012-02-06T20:17:35Z 2014-03-28T10:00:13Z 2011-12 2012-02-06T20:17:35Z 2011-12 Coverage analysis is critical in pre-silicon verification of hardware designs for assessing the completeness of verification and identifying inadequately exercised areas of the design. It is widely integrated in the simulation based verification flow in the hardware industry. In this thesis, we provide solutions to enable effective coverage analysis in assertion based and emulation based verification. We introduce two practical and effective code coverage metrics for assertions: one inspired by the test suite code coverage reported by Register Transfer Level (RTL) simulators and the other by assertion correctness in the context of formal verification. We present efficient algorithms to compute coverage with respect to the proposed metrics by analyzing the Control Flow Graph (CFG) constructed from the RTL source code. We apply our technique to a USB 2.0 design and an OpenRISC processor design and show that our coverage evaluation is efficient and scalable. We also present a technique to evaluate and rank automatically generated assertions based on fault coverage. We present a novel technique to extract code coverage from emulation platforms. Using our CFG framework, we identify conditions or decision nodes and map them to other statements in the code. Triggering of decision nodes is recorded using additional trigger logic during emulation and mapped back to the source code to obtain coverage information. We apply our technique to an industrial design and show that it can efficiently provide fairly accurate code coverage statistics with minimal overheads during emulation. Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2011-11-29T21:45:55Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Athavale_VirajMilind.pdf: 1581882 bytes, checksum: e492a06be78bb842c0615144c6d0c3e6 (MD5) Athavale_Viraj.pdf: 1581882 bytes, checksum: e492a06be78bb842c0615144c6d0c3e6 (MD5) Made available in DSpace on 2012-02-06T20:17:35Z (GMT). No. of bitstreams: 2 Athavale_Viraj.pdf: 1581882 bytes, checksum: e492a06be78bb842c0615144c6d0c3e6 (MD5) license.txt: 4064 bytes, checksum: dc5a5f7720b8aa6180eb55d611399e9d (MD5) Item marked as restricted to the 'Administrator' Group (id=1) by Sarah Shreeves (sshreeve@illinois.edu) on 2012-03-27T20:49:43Z Item is restricted until 2014-03-27T20:49:43Z Item reinstated by Sarah Shreeves (sshreeve@illinois.edu) on 2014-03-28T10:00:12Z Item was in collections: Graduate Theses and Dissertations at Illinois (ID: 204) Dissertations and Theses - Electrical and Computer Engineering (ID: 446) No. of bitstreams: 3 Athavale_Viraj.pdf.txt: 145732 bytes, checksum: 76b527d37db9caebaea41bed45637663 (MD5) Athavale_Viraj.pdf: 1581882 bytes, checksum: e492a06be78bb842c0615144c6d0c3e6 (MD5) license.txt: 4064 bytes, checksum: dc5a5f7720b8aa6180eb55d611399e9d (MD5) Item released from any restrictions by Sarah Shreeves (sshreeve@illinois.edu) on 2014-03-28T10:00:13Z http://hdl.handle.net/2142/29795 en Copyright 2011 Viraj Athavale pre-silicon verification coverage assertions emulation code coverage fault coverage static analysis Coverage analysis for assertions and emulation based verification Dissertation / Thesis text Electrical & Computer Eng 1933 Electrical & Computer Engr 1200 University of Illinois at Urbana-Champaign Thesis M.S. MS:Electr & Computer Eng-UIUC 10KS1200MS