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oai:www.ideals.illinois.edu:2142/34229 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Schutt-Ainé, José E. Win, Si 2012-09-18T21:06:54Z 2012-09-18T21:06:54Z 2012-08 2012-09-18T21:06:54Z 2012-08 Due to timing issues created by high speed applications, simulation of in- put/output (I/O) buffers with an emphasis on signal integrity has been an important aspect in the design of integrated circuits (IC). Simulation of I/O buffers however proved to be quite difficult. For vendors it would mean releasing proprietary information about their I/O buffers which would not only include a full transistor-level schematic but also full process informa- tion such as transistor oxide thickness. In addition, for designers to perform a full transistor-level simulation it would take hours using traditional circuit simulators such as SPICE. This led to the development of input/output buffer information specifica- tion (IBIS) which was developed at Intel to overcome these obstacles. IBIS uses a behavioral modeling method that is based on I-V and V-t curves ob- tained from either direct measurements or circuit simulations. This provided designers with a model that contains nonproprietary information about I/O buffers and provided a fast alternative method to full transistor-level simu- lations. In this thesis we will show how to simulate IBIS models using traditional circuit simulators: specifically Synopsys HSpice and Agilent Advanced De- sign System (ADS). IBIS has become widely accepted in industry due to the fact that it protects the intellectual property of vendors and because of its standardized format which allows it to be integrated with many circuit simulators. Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-07-18T17:12:57Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Thesis.zip: 1241628 bytes, checksum: 80b35131620bcab77db20fcbc87b9f06 (MD5) Win_Si.pdf: 921901 bytes, checksum: e5d99cde8e9c6c165e77cdff2af4fe39 (MD5) Made available in DSpace on 2012-09-18T21:06:54Z (GMT). No. of bitstreams: 3 Win_Si.pdf: 921901 bytes, checksum: e5d99cde8e9c6c165e77cdff2af4fe39 (MD5) license.txt: 4054 bytes, checksum: 340d7b3c7bfb613f74bfe395f528ea9e (MD5) Thesis.zip: 1241628 bytes, checksum: 80b35131620bcab77db20fcbc87b9f06 (MD5) http://hdl.handle.net/2142/34229 en Copyright 2012 Si Win input/output buffer information specification (IBIS) Simulation Simulation of IBIS models using HSpice and ADS Electrical & Computer Eng 1933 Electrical & Computer Engr 1200 University of Illinois at Urbana-Champaign Thesis M.S. MS:Electr & Computer Eng-UIUC 10KS1200MS