2026-09-19T17:15:24Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/34230 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

2012-08 2012-09-18T21:06:58Z Chen, Deming Chen, Ying-Yu 2012-09-18T21:06:58Z 2012-09-18T21:06:58Z 2012-08 In this thesis, we propose a maze-routing-based clock tree routing algorithm integrated with buffer insertion, buffer sizing, and topology generation that is able to consider general buffer insertion locations. While previous work on buffered clock tree synthesis restricts potential buffer locations on merge nodes in the clock tree topology, our proposed algorithm has more freedom and thus achieves more robust slew control. Buffer insertion along routing paths had been mostly avoided previously due to the difficulty of maintaining a low skew under such aggressive buffer insertion. We developed an accurate timing analysis engine for delay and slew estimations and a balanced routing scheme for better skew reduction during clock tree synthesis. As a result, we can perform aggressive buffer insertion and maintain accurate delay information and low skew. Buffer sizing is also guided by its performance for slew control. Experiments show that our synthesis results not only honor the slew constraints but also maintain reasonable skew. Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-07-18T22:19:50Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 5 ecethesis.bib: 14826 bytes, checksum: 83f626c307907f8f6363e69e3373faf6 (MD5) ack.tex: 388 bytes, checksum: 61d2e008d4ea9e6c3220cbdd339f0b0d (MD5) abs.tex: 1042 bytes, checksum: 9c809687260ffe78e5f20caec327025f (MD5) ecethesis_v1.2.tex: 48081 bytes, checksum: b18d5ace2a6ee01cfce1bbb881ebe12b (MD5) Chen_Ying-Yu.pdf: 2018909 bytes, checksum: 73b6c3678bc56e6f01876a66acf8a06c (MD5) Made available in DSpace on 2012-09-18T21:06:58Z (GMT). No. of bitstreams: 6 Chen_Ying-Yu.pdf: 2018909 bytes, checksum: 73b6c3678bc56e6f01876a66acf8a06c (MD5) license.txt: 4058 bytes, checksum: 09094a912ca7a8c1e57dba1a4a4e5f25 (MD5) ecethesis_v1.2.tex: 48081 bytes, checksum: b18d5ace2a6ee01cfce1bbb881ebe12b (MD5) abs.tex: 1042 bytes, checksum: 9c809687260ffe78e5f20caec327025f (MD5) ack.tex: 388 bytes, checksum: 61d2e008d4ea9e6c3220cbdd339f0b0d (MD5) ecethesis.bib: 14826 bytes, checksum: 83f626c307907f8f6363e69e3373faf6 (MD5) http://hdl.handle.net/2142/34230 en Copyright 2012 Ying-Yu Chen Clock Tree Buffer Insertion Buffer Sizing Maze Routing Slew Clock tree synthesis under aggressive buffer insertion Electrical & Computer Eng 1933 Electrical & Computer Engr 1200 University of Illinois at Urbana-Champaign Thesis M.S. PHD:Electr & Computer Eng-UIUC 10KS1200PHD