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oai:www.ideals.illinois.edu:2142/34585 2023-07-11 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

Torrellas, Josep Jain, Prabhat 2012-09-18T21:26:44Z 2012-09-18T21:26:44Z 2014-09-18T10:00:47Z 2012-08 2012-09-18T21:26:44Z 2012-08 As manycores use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low voltage, leakage in on-chip memory modules contributes substantially to the chip’s power draw. This is unfortunate given that, intuitively, the large multi-level cache hierarchy of a manycore is likely to contain a lot of useless data. An effective way to reduce this problem is to use a low-leakage technology such as embedded DRAM (eDRAM). However, such systems require refresh. In this paper, we examine the opportunity of minimizing on-chip memory power by intelligently refreshing a full-eDRAM cache hierarchy. We present Refrint, a simple approach to perform fine-grained, intelligent refresh of eDRAM multiprocessor cache hierarchies. We introduce the Refrint algorithms and the microarchitecture support. We evaluate Refrint in a simulated manycore running 16-threaded parallel applications. Compared to a full-SRAM system, Refrint’s memory hierarchy only consumes 36% of the SRAM’s memory hierarchy energy and induces a negligible slowdown. In contrast, a basic full-eDRAM memory hierarchy consumes 50% of the SRAM’s memory hierarchy energy and induces a slowdown of 18%. Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-06-26T13:56:30Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Jain_Prabhat.pdf: 355209 bytes, checksum: ef80450a373f000c9166985536a835f4 (MD5) Made available in DSpace on 2012-09-18T21:26:44Z (GMT). No. of bitstreams: 2 Jain_Prabhat.pdf: 355210 bytes, checksum: 6b3a29b6cfadd289965c035e7ce2b153 (MD5) license.txt: 4060 bytes, checksum: bbd0e2d932eaec1d0ebeb3f95275ef68 (MD5) Item marked as restricted to the 'Administrator' Group (id=1) by Seth Robbins (srobbins@illinois.edu) on 2012-09-18T21:27:37Z Item is restricted until 2014-09-18T21:27:16Z Restriction data tranferred 2014-07-01T11:35:55-05:00 Original Data Group with Access Administrator Release Date: 2014-09-18 16:27:16 UTC Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Limited Restriction Lifted for Item 34859 on 2014-09-18T10:00:47Z. http://hdl.handle.net/2142/34585 en Copyright 2012 Prabhat Jain Static random-access memory (SRAM) Embedded dynamic random-access memory (eDRAM) memory hierarchy computer architecture leakage refresh power Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies Computer Science 1434 Computer Science 0112 University of Illinois at Urbana-Champaign Thesis M.S. MS:Computer Science -UIUC 10KS0112MS