2026-09-18T21:00:46Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/42300 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

simulation Schutt-Ainé, José E. Bhagat, Karan 2013-02-03T19:30:47Z 2013-02-03T19:30:47Z 2012-12 2013-02-03T19:30:47Z 2012-12 Many telecommunication applications require a fast switching, fine tuning and superior quality sinusoidal signal source for their components. One such a frequency synthesizer is a direct digital synthesizer (DDS). This thesis work utilizes a design that aims to combine digital circuit design and electronic communication knowledge, and apply them in a practical environment. It does so by providing a tutorial on designing and implementing a DDS on an FPGA using Xilinx’s ISE software. The thesis also examines the final results and shows the unwanted spurs that are generated. Since this is purely a digital design, it does not implement a digital-to-analog converter (DAC) or a low-pass filter. Using a Virtex 6 design for the FPGA, one can achieve close to perfect sinusoids, without any phase change, with varying frequency tuning words (FTWs). Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-12-04T22:02:14Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Bhagat_Karan.docx: 2913460 bytes, checksum: eb4a8698b56e29f7a8fe973ca9d335aa (MD5) Bhagat_Karan.pdf: 2413441 bytes, checksum: a540bdcf7c20875657ab23053c6fad0c (MD5) Made available in DSpace on 2013-02-03T19:30:47Z (GMT). No. of bitstreams: 3 Karan_Bhagat.pdf: 2413441 bytes, checksum: a540bdcf7c20875657ab23053c6fad0c (MD5) Bhagat_Karan.docx: 2913460 bytes, checksum: eb4a8698b56e29f7a8fe973ca9d335aa (MD5) license.txt: 4062 bytes, checksum: 81a7d7f365617cc4f4b80ae7c87d0742 (MD5) http://hdl.handle.net/2142/42300 en Copyright 2012 Karan Bhagat direct digital synthesis (DDS) direct digital synthesizer direct digital synthesizer (DDS) Field-Programmable Gate Array (FPGA) circuit design digital circuit design design flow design Implementation Verilog tutorial phase accumulator sine lookup table phase truncation spurs place and route ModelSim Xilinx Virtex Tutorial on designing and implementing a direct digital synthesizer (DDS) on a field programmable gate array (FPGA) text Electrical & Computer Eng 1933 Electrical & Computer Engr 1200 University of Illinois at Urbana-Champaign Thesis M.S. MS:Electr & Computer Eng-UIUC 10KS1200MS