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        <identifier>oai:www.ideals.illinois.edu:2142/42360</identifier>
        <datestamp>2023-07-11</datestamp>
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          <dc:contributor>Shanbhag, Naresh R.</dc:contributor>
          <dc:creator>Zhang, Sai</dc:creator>
          <dc:date>2013-02-03T19:36:22Z</dc:date>
          <dc:date>2013-02-03T19:36:22Z</dc:date>
          <dc:date>2012-12</dc:date>
          <dc:date>2013-02-03T19:36:22Z</dc:date>
          <dc:date>2012-12</dc:date>
          <dc:description>Switched capacitor voltage regulator module (SC-VRM) is suitable for low power embedded systems operating in near/sub-threshold region due to its high conversion ratio and compactness. However, existing optimization for SC-VRM is separated from the embedded core design and therefore leads to sub-optimal system energy efficiency. In this thesis, we propose to jointly optimize the switched capacitor voltage regulator module (SC-VRM) and the compute core to minimize system energy per instruction. A core-aware SC-VRM energy model is developed and employed to solve the joint optimization problem. We also propose and optimize a reconfigurable SC-VRM architecture. Simulation results in a 130nm CMOS process indicate that the core-aware SC-VRM model predicts energy from circuit simulations to within 5%, and that the proposed approach results in a maximum system energy savings of 8% to 38.9%. The reconfigurable SC-VRM achieves 15% to 52% energy saving as compared to an efficiency-optimized design.</dc:description>
          <dc:description>Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-12-11T13:55:15Z
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          <dc:identifier>http://hdl.handle.net/2142/42360</dc:identifier>
          <dc:language>en</dc:language>
          <dc:rights>Copyright 2012 Sai Zhang</dc:rights>
          <dc:subject>Switched capacitor voltage regulator module</dc:subject>
          <dc:subject>Sub/near-threshold operation</dc:subject>
          <dc:subject>Optimization</dc:subject>
          <dc:subject>Low power design</dc:subject>
          <dc:title>System-level optimization of the DC-DC voltage regulator and core for sub/near-threshold voltage operation</dc:title>
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            <department>Electrical &amp; Computer Eng</department>
            <departmentCode>1933</departmentCode>
            <discipline>Electrical &amp; Computer Engr</discipline>
            <disciplineCode>1200</disciplineCode>
            <grantor>University of Illinois at Urbana-Champaign</grantor>
            <level>Thesis</level>
            <name>M.S.</name>
            <program>PHD:Electr &amp; Computer Eng-UIUC</program>
            <programCode>10KS1200PHD</programCode>
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