2026-09-22T03:12:38Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/44439 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Chen, Deming Tolar, Jacob 2013-05-24T22:16:11Z 2013-05-24T22:16:11Z 2015-05-24T10:01:49Z 2013-05 2013-05-24T22:16:11Z 2013-05 This thesis presents and evaluates a directory enhanced network on chip for FPGA, with the goal of improving the performance of cores generated by FCUDA, a translation tool enabling CUDA code to be run on FGPAs. NoCs are an inherently scalable platform, as aggregate system bandwidth increases with the number of nodes in the system. This work enhances an existing NoC to include a directory protocol capable of tracking the location of on-chip data stored in core-local BRAMs. By tracking the location of on-chip data, requests that would normally be satisfied by o↵-chip memory can be fulfilled by on-chip sources, allowing performance gains. Simulation results show a directory-enhanced NoC gains of up to 40% in speed over an ordinary NoC for some applications. In addition, simulation and synthesis results show potential for increased overall application performance over a bus-based system, despite the significant area overhead of NoC routers. Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2013-04-23T17:04:13Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Tolar_Jacob.pdf: 1210591 bytes, checksum: 7e129ce8b9b4e808c881e496fd480163 (MD5) Made available in DSpace on 2013-05-24T22:16:11Z (GMT). No. of bitstreams: 2 Jacob_Tolar.pdf: 1251086 bytes, checksum: 32575a7651cea1a523309b10bd7a0f09 (MD5) license.txt: 4061 bytes, checksum: bf4d80ddd86a81fd6a9b64ef93e5841b (MD5) Restriction data tranferred 2014-07-01T11:36:10-05:00 Original Data Group with Access UIUC Users [automated] Release Date: 2015-05-24 17:18:31 UTC Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Seth Robbins (srobbins@illinois.edu) on 2013-05-24T22:18:55Z Item is restricted until 2015-05-24T22:18:31Z U of I Only Restriction Lifted for Item 44412 on 2015-05-24T10:01:49Z. http://hdl.handle.net/2142/44439 en Copyright 2013 Jacob Tolar Network on Chip Field-Programmable Gate Array (FPGA) FCUDA A directory enhanced network on chip for FPGA text Electrical & Computer Eng 1933 Electrical & Computer Engr 1200 University of Illinois at Urbana-Champaign Thesis M.S. MS:Electr & Computer Eng-UIUC 10KS1200MS