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Mayeda, Watura Robbins, David H. 2013-09-09T15:47:22Z 2013-09-09T15:47:22Z 1975 Optimization of size is an important topic of research in the engineering of digital circuits. The field effect transistor (FET) is making an important contribution in this area. In this paper, the basic properties of the FET which pertain to digital circuits will be examined. The problems associated with the physical layout of large integrated circuits using FETs will also be discussed and a standardized method of layout will be reviewed. A simple procedure for optimizing chip area when using this standardized layout method will be developed and illustrated. Submitted by Sarah Shreeves (sshreeve@illinois.edu) on 2013-09-09T15:47:22Z No. of bitstreams: 1 Robbins_David.pdf: 785749 bytes, checksum: ed4500e106461d73bd0e229e4128ab0a (MD5) Made available in DSpace on 2013-09-09T15:47:22Z (GMT). No. of bitstreams: 1 Robbins_David.pdf: 785749 bytes, checksum: ed4500e106461d73bd0e229e4128ab0a (MD5) Previous issue date: 1975 http://hdl.handle.net/2142/45707 en Copyright 1975 David H. Robbins Field Effect Transistor (FET) Optimum gate arrangements for MOS standardized layouts text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Thesis M.S.