2026-09-19T21:08:00Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/49624 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Rosenbaum, Elyse Mertens, Robert 2014-05-30T16:52:57Z 2014-05-30T16:52:57Z 2014-05 2014-05-30T16:52:57Z 2014-05 This thesis presents an SCR compact model for simulating ESD protection circuits. The aspects of the compact model that are necessary to reproduce measurement data, such as quasi-static I-V curves and transient voltage overshoot, are discussed. These aspects include conductivity modulation of the well resistances in the SCR, impact ionization at the N-well/P-well junction, and the influence of electric fields in the well region on carrier diffusion between the anode and cathode. Further, a detailed validation of the compact model is presented. A methodology for parameter extraction is also discussed. Item withdrawn by Laura Spradlin (lspradl2@illinois.edu) on 2014-02-12T14:36:16Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Mertens_Robert.docx: 1319696 bytes, checksum: 87772c98205a345c99f1ba2b49eb41e8 (MD5) Mertens_Robert.pdf: 1728639 bytes, checksum: f74ff9d138a485b3bd2b50422dcf8048 (MD5) Made available in DSpace on 2014-05-30T16:52:57Z (GMT). No. of bitstreams: 3 Robert_Mertens.pdf: 1728639 bytes, checksum: f74ff9d138a485b3bd2b50422dcf8048 (MD5) Mertens_Robert.docx: 1319696 bytes, checksum: 87772c98205a345c99f1ba2b49eb41e8 (MD5) license.txt: 4064 bytes, checksum: d245e18157761781554dbc2b10e5db55 (MD5) http://hdl.handle.net/2142/49624 en Copyright 2014 Robert Mertens Complementary metal–oxide–semiconductor (CMOS) integrated circuits silicon silicon controlled rectifiers (SCR) Electrostatic discharge (ESD) A compact model for silicon controlled rectifiers in low voltage CMOS processes text Electrical & Computer Eng 1933 Electrical & Computer Engr 1200 University of Illinois at Urbana-Champaign Thesis M.S. MS:Electr & Computer Eng-UIUC 10KS1200MS