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Patel, Janak H. Eickemeyer, Richard James 2014-12-15T19:05:29Z 2014-12-15T19:05:29Z 10000-01-01 1988 1988 Multiple register set architectures have been proposed as a method to reduce the large amount of memory traffic associated with high-level language procedure calls. In this thesis, the effect on overall processor memory traffic of multiple register sets is characterized for a set of real programs. To accomplish this, traces of programs' address and register references were collected on a VAX-11/780. These traces were then mapped to the traces that could have come from a hypothetical VAX with multiple register sets. The memory traffic for various numbers of register sets and numbers of registers per set were compared to the memory traffic in the original trace. The results show a 10-20% reduction in memory traffic using the multiple register sets; the results vary among programs. The effect of context switch was also measured and found not to be significant. A synthetic benchmark program, Dhampstone, was written in the C language with the goal to accurately characterize program behavior with and without multiple register sets. To construct the program, existing program statistics were supplemented with measurements of I/O and C language register declarations. The change in memory traffic with multiple register sets on Dhampstone was compared to the change measured in the real programs; there was good agreement for a variety of numbers of sets and numbers of registers per set. Multiple register sets were compared to other local memory organizations using a chip area model and a memory access time model. These organizations consisted of a variety of different cache organizations. Combinations of different caches and multiple register sets were also examined. With a small chip area, a top-of-stack cache performed better than multiple register sets. For larger chip areas, an instruction cache, or better yet, an instruction cache plus a small top-of-stack cache, perform well. At the largest cache sizes studied, a full cache is required, so that each memory reference could potentially be in the cache. Adding multiple register sets to a full cache improves performance slightly for larger chip areas. Made available in DSpace on 2014-12-15T19:05:29Z (GMT). No. of bitstreams: 1 8815338.pdf: 4366809 bytes, checksum: 314edc87ca512bf7aef280866fd90c6b (MD5) Previous issue date: 1988 Embargo set by: Seth Robbins for item 69549 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 109 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988. http://hdl.handle.net/2142/69383 (UMI)AAI8815338 Engineering, Electronics and Electrical Computer Science Performance Evaluation of Multiple Register Set Architectures and Cache Memories text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.