2026-09-19T15:23:35Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/69391 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Hajj, Ibrahim N. Tejayadi, Ongky 2014-12-15T19:05:32Z 2014-12-15T19:05:32Z 10000-01-01 1988 1988 The work presented in this thesis deals with the development of a fast and fairly accurate Computer Aided Design software for simulating very-large-scale-integrated (VLSI) circuits. The methods rely on piecewise linearized nonlinear elements in the circuits. The piecewise linear approaches explored in this work are (1) A fast piecewise linear Gauss-Seidel waveform relaxation method. (2) A slower but more accurate piecewise linear method based on simplices. (3) A Gauss-Seidel piecewise linear method with dynamic partitioning. Also described in a mixed method which combines the fast piecewise linear method and the dynamic partitioning method. The circuit to be analyzed is partitioned into dc-connected subcircuits and then sequenced for analysis. Small subcircuits are solved using the fast piecewise linear method while large subcircuits, including the strongly-connected components in the circuit, are solved using the dynamic partitioning method. A parallel implementation of the Gauss-Seidel piecewise linear method with dynamic partitioning on a uniprocessor computer is studied. Algorithms for the parallel implementation of the dynamic partitioning approach on a multiprocessor with shared memory (Alliant FX/8) are also explained in detail. The piecewise linear methods presented in this work have been implemented in a set of programs called PLATINUM. The waveforms generated by PLATINUM are fairly accurate as compared to SPICE2, and the speedup for a uniprocessor machine is over two orders of magnitude, while the parallel implementation gives an additional 4 to 6 times speed improvements. Made available in DSpace on 2014-12-15T19:05:32Z (GMT). No. of bitstreams: 1 8815430.pdf: 3747772 bytes, checksum: acdc618071bcb24e9f4430701dc0f2a5 (MD5) Previous issue date: 1988 Embargo set by: Seth Robbins for item 69557 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 139 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988. http://hdl.handle.net/2142/69391 (UMI)AAI8815430 Engineering, Electronics and Electrical Computer Science Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.