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Krolikoski, Stanley Joseph 2014-12-15T19:25:39Z 2014-12-15T19:25:39Z 10000-01-01 1985 1985 Turn-around time is becoming a crucial problem in integrated circuit design. Thus, Programmable Logic Arrays (PLA's) have become popular means with which to implement circuits. Their regular (i.e., matrix) structure allows for easy initial design and quick changes at later stages of design. PLA's, however, waste space, and so some method for reducing them has been sought. The SQUEEZE algorithm is used in reducing PLA's. It does not guarantee the minimality of its results, but it is able to produce near minimal results in a reasonable amount of cpu time. The thesis is divided into three main sections. First, there is an introduction to PLA's. Next there is an in-depth discussion of SQUEEZE. Finally, there are statistics presented which indicate the actual performance of the programs which implement SQUEEZE. Made available in DSpace on 2014-12-15T19:25:39Z (GMT). No. of bitstreams: 1 8521810.pdf: 5289753 bytes, checksum: d1b56149874e40bcb11080a576f27cea (MD5) Previous issue date: 1985 Embargo set by: Seth Robbins for item 69708 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 205 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985. http://hdl.handle.net/2142/69542 (UMI)AAI8521810 Computer Science The Squeeze Algorithm for Pla Minimization (Logic, Computer-Aided, Circuit Design) text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.