2026-09-21T04:23:40Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/73003 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Rosenbaum, Elyse Xiu, Yang 2015-01-21T19:55:57Z 2015-01-21T19:55:57Z 2017-01-22T10:15:29Z 2014-12 2015-01-21 2014-12 In this thesis, we will describe an experimental study of one possible soft failure mechanism during power-on electrostatic discharge (ESD). For contact discharge into a test chip mounted on a board, logic upsets can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. This type of upset often involves contention between the transistor and the parasitic structure. Therefore, the likelihood for logic upsets to occur is sensitive to transistor sizing, as well as the collection efficiency of the parasitic structure. The collection efficiency is affected by various factors, including spacing and collector size. The occurrence of logic upsets is dependent on the ESD pulse injected. They are observed during transmission line pulses of various widths, where the upset pattern changes according to the pulse width. Upsets are also observed during system-level ESD tests, such as the ISO 10605 stress. Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2014-12-01T20:57:31Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Xiu_Yang.pdf: 1248572 bytes, checksum: 2e329e82ee2456a54c6caa2693b35a5d (MD5) Made available in DSpace on 2015-01-21T19:55:57Z (GMT). No. of bitstreams: 1 Yang_Xiu.pdf: 1248572 bytes, checksum: 2e329e82ee2456a54c6caa2693b35a5d (MD5) Embargo set by: Seth Robbins for item 73192 Lift date: 2017-01-21T19:56:18Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system U of I Only Restriction Lifted for Item 73192 on 2017-01-22T10:15:29Z. http://hdl.handle.net/2142/73003 en Copyright 2014 Yang Xiu power-on electrostatic discharge (ESD) soft failure substrate current system-level electrostatic discharge (ESD) Logic upset induced by substrate current during power-on ESD text Electrical & Computer Eng 1933 Electrical & Computer Engr 1200 University of Illinois at Urbana-Champaign Thesis M.S. MS:Electr & Computer Eng-UIUC 10KS1200MS