2026-09-21T19:59:44Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/73090 2023-07-11 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

Torrellas, Josep Pothukuchi, Raghavendra Pradyumna 2015-01-21T19:59:26Z 2015-01-21T19:59:26Z 2017-01-22T10:15:32Z 2014-12 2015-01-21 2014-12 Networks-on-Chip (NoCs) are prone to within-die process variation as they span the whole chip. To tolerate variation, their voltages (Vdd) carry overprovisioned guardbands. As a result, prior work has proposed to save energy by dynamically managing Vdd, operating at reduced Vdd while occasionally su ering and xing errors. Unfortunately, these proposals use ad-hoc controller designs that may not work under other scenarios and do not provide error bounds. This thesis develops a scheme that dynamically minimizes the Vdd of groups of routers in a variation-prone NoC using formal control-theory methods. The scheme, called Contra, saves substantial energy while guaranteeing the stability and convergence of error rates. Moreover, the scheme is enhanced with a low-cost secondary network that retransmits erroneous packets for higher energy e ciency. The enhanced scheme is called Contra+. Both Contra and Contra+ are evaluated using simulations of NoCs with 64{100 routers. In an NoC with 8 routers per Vdd domain, the proposed schemes reduce the average energy consumption of the NoC by 27%; in a futuristic NoC with one router per Vdd domain, Contra+ and Contra reduce the average energy consumption by 37% and 32%, respectively. The performance impact is negligible. These savings are signi cant over the state-of-the-art. The results categorically state that formal control is essential to attain a stable, scalable, and energy-efficient design. Additionally, it is found that while the secondary network helps Contra+ attain higher energy savings, it has a nonnegligible hardware cost. Hence, Contra is the most cost-effective design. Item withdrawn by Laura Spradlin (lspradl2@illinois.edu) on 2014-12-05T17:11:52Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Pothukuchi_Raghavendra Pradyumna.pdf: 2697519 bytes, checksum: c06e93f9a071c02f989c1ba7581242d1 (MD5) Pothukuchi_Raghavendra Pradyumna.pdf: 2697510 bytes, checksum: de24e3ad8adcd82236bb0bab0b9e9c58 (MD5) Made available in DSpace on 2015-01-21T19:59:26Z (GMT). No. of bitstreams: 1 Raghavendra Pradyumna_Pothukuchi.pdf: 2689844 bytes, checksum: 72bd35d68426515996fc837fdba12b2d (MD5) Embargo set by: Seth Robbins for item 73279 Lift date: 2017-01-21T19:59:39Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Limited Restriction Lifted for Item 73279 on 2017-01-22T10:15:32Z. http://hdl.handle.net/2142/73090 en Copyright 2014 Raghavendra Pradyumna Pothukuchi Computer Architecture Reliability Energy efficiency Systematically controlling the error rates in variation-prone networks-on-chip for energy efficiency text Computer Science 1434 Computer Science 0112 University of Illinois at Urbana-Champaign Thesis M.S. MS:Computer Science -UIUC 10KS0112MS