2026-09-18T19:12:45Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/78571 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Vissa, Pranay 2015-07-22T22:18:21Z 2015-07-22T22:18:21Z 2015-05 2015-05-01 2015-5 With transistor dimensions shrinking to the atomic scale, a plethora of new reliability problems presents a barrier to continued Moore’s law scaling. Traditional modular redundancy techniques with 2x and 3x area cost eliminate the area reduction benefits of such scaling. In this study, we take a partial redundancy approach to the reliability problem for arithmetic-orientated datapaths by performing lightweight shadow computations in the mod-b space, where b is the base of our modulo residue, for each main computation. We leverage the binding and scheduling flexibility of high-level synthesis to detect control errors through diverse binding and minimize area cost through intelligent checkpoint scheduling and modulo-b reducer sharing. We introduce logic and dataflow optimizations to further reduce cost. We evaluated our technique with 12 high-level synthesis benchmarks from the arithmetic- oriented PolyBench benchmark suite using FPGA emulated netlist-level error injection. When b = 3, we observe coverages of 99.2% for stuck-at faults, 99.5% for soft errors, and 99.8% for timing errors with a 25.7% area cost and negligible performance impact. When b = 5, we observe coverages of 99.4% for stuck-at faults, 99.8% for soft errors, and 99.9% for timing errors with a 48.5% area cost and negligible performance impact. Leveraging a mean error detection latency of 13.92 and 14.96 cycles, with both mod-3 and mod-5 units respectively (2554x faster than end result check) for soft errors, we also explore a rollback recovery method with an additional area cost of 28.0% for both cases, observing 411x increase in reliability against soft errors. Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2015-07-22 without embargo terms The student, Pranay Vissa, accepted the attached license on 2015-05-01 at 10:27. The student, Pranay Vissa, submitted this Thesis for approval on 2015-05-01 at 10:36. This Thesis was approved for publication on 2015-05-01 at 10:47. DSpace SAF Submission Ingestion Package generated from Vireo submission #8227 on 2015-07-22 at 10:35:19 Made available in DSpace on 2015-07-22T22:18:21Z (GMT). No. of bitstreams: 2 VISSA-THESIS-2015.pdf: 1055593 bytes, checksum: 616a928d6d7403a807b2578e9e2476fc (MD5) LICENSE.txt: 4209 bytes, checksum: b91301cd9a646137496f708d1dc58fa6 (MD5) Previous issue date: 2015-05-01 application/pdf http://hdl.handle.net/2142/78571 en Copyright 2015 Pranay Vissa high-level synthesis automation error detection scheduling binding optimization pipelining modulo arithmetic logic optimization state machine datapath shadow logic low cost high performance electrical faults Aliasing stuck-at faults soft errors timing errors checkpointing rollback recovery Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.