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oai:www.ideals.illinois.edu:2142/78602 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Gao, Tianqi 2015-07-22T22:33:13Z 2015-07-22T22:33:13Z 2017-07-23T09:15:28Z 2015-05 2015-04-07 Increasingly severe parameter variations that are observed in advanced nanoscale technologies create great obstacles in designing high-performance, next-generation digital integrated circuits (ICs). Conventional design principles impose increased design margins in power supply, device sizing, and operating frequency, leading to overly conservative designs which prevent the realization of potential benefits from nanotechnology advances. In response, robust digital circuit design techniques have been developed to overcome processing non-idealities. Statistical error compensation (SEC) is a class of system-level, communication-inspired techniques for designing energy efficient and robust systems. In this thesis, stochastic sensor network on chip (SSNOC), a known SEC technique, is applied to a computational kernel implemented with carbon nanotube field-effect transistors (CNFETs). With the aid of a well developed CNFET delay distribution modeling method, circuit simulations show up to 90× improvement of the SSNOC-based design in the circuit yield over the conventional design. The results verify the robustness of an SEC-based design under CNFET-specific variations. The error resiliency of SEC allows CNFET circuits to operate with reduced design margins under relaxed processing requirements, while concurrently maintaining the desired application-level performance. Submission published under a 24 month embargo labeled 'U of I only', the embargo will last until 2017-05-01 The student, Tianqi Gao, accepted the attached license on 2015-04-07 at 13:06. The student, Tianqi Gao, submitted this Thesis for approval on 2015-04-07 at 13:17. This Thesis was approved for publication on 2015-04-07 at 15:27. DSpace SAF Submission Ingestion Package generated from Vireo submission #7800 on 2015-07-22 at 14:17:38 2015-5 Made available in DSpace on 2015-07-22T22:33:13Z (GMT). No. of bitstreams: 2 GAO-THESIS-2015.pdf: 1277115 bytes, checksum: 9c20528d827fdfc8723ea53970504412 (MD5) LICENSE.txt: 4207 bytes, checksum: 99c19c867bb453d1877453bd847f2df6 (MD5) Previous issue date: 2015-04-07 Embargo set by: Seth Robbins for item 79843 Lift date: 2017-07-22T22:34:16Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system U of I Only Restriction Lifted for Item 79843 on 2017-07-23T09:15:28Z. application/pdf http://hdl.handle.net/2142/78602 en Copyright 2015 Tianqi Gao variation-tolerant techniques power-efficient design emerging technologies error compensation Overcoming nanoscale variations through statistical error compensation text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.