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oai:www.ideals.illinois.edu:2142/78689 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Zhu, Lida 2015-07-22T22:34:02Z 2015-07-22T22:34:02Z 2017-07-23T09:15:30Z 2015-05 2015-04-30 In this project, the modeling of gate current is introduced to obtain a negative differential resistance (NDR) on a dual-channel tunneling real-space transfer transistor (TRSTT). The device was fabricated on a GaAs (100) substrate with a GaAs/InGaAs/GaAs straddling heterostructure. According to the experimental data reported by Yu et al. in 2010 [1], they demonstrate an InGaAs and \delta-doped GaAs dual-channel TRSTT device with an \lambda-type NDR in a low drain-source voltage (VDS), which reaches a peak-to-valley current ratio of 3.3. Meanwhile, the gate-source current sharply increases at the same applied VDS. The thesis aims to build current models to reproduce these I-V characteristics, and to investigate the mechanism of current-controllable NDR effects. The drain-source I-V relation without leakage has been first derived and simulated to fit the experimental data and set down constants for later modeling processes. Then an analytic model of the gate current IG is introduced. The simulated results obtained a sharp drop similar to experimental data. The gate current model involves intermediate modeling processes such as tunnel probability (\theta_y), velocity of charges (\upsilon_y) approach to quantum well (QW), charge distribution function (f(E)), and potential difference along the channel (V (x)). These models are discussed in a progressive path step by step, which includes numerical derivation and simulations. The current flow direction will be analyzed as a core point. The complementary drain-source I-V characteristic relation is produced by considering the gate current derived before and generating a family of curves in a \lambda-shaped NDR in the same VDS region with a sharp drop of IG. All the simulations are done by mathematical iterating in Matlab with the Illinois Taub Cluster as simulator source. The simulated results will be compared with experimental data to verify the high reliability of the model. In the last section of the project, the limitation of the uncomplementary derivation of V (x) after device saturation will be discussed, accompanied by suggestions for future improvements. Submission published under a 24 month embargo labeled 'U of I only', the embargo will last until 2017-05-01 The student, Lida Zhu, accepted the attached license on 2015-04-29 at 13:34. The student, Lida Zhu, submitted this Thesis for approval on 2015-04-29 at 14:02. This Thesis was approved for publication on 2015-04-30 at 10:07. DSpace SAF Submission Ingestion Package generated from Vireo submission #8187 on 2015-07-22 at 14:19:03 Made available in DSpace on 2015-07-22T22:34:02Z (GMT). No. of bitstreams: 2 ZHU-THESIS-2015.pdf: 1675674 bytes, checksum: 2f0b4e8d24310360b1c9e82a7d499713 (MD5) LICENSE.txt: 4205 bytes, checksum: fa6dad42aa41d1562c9565e8af78cfcd (MD5) Previous issue date: 2015-04-30 2015-5 Embargo set by: Seth Robbins for item 79930 Lift date: 2017-07-22T22:34:16Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system U of I Only Restriction Lifted for Item 79930 on 2017-07-23T09:15:30Z. application/pdf http://hdl.handle.net/2142/78689 en Copyright 2015 Lida Zhu negative differential resistance (NDR) tunneling real-space transfer transistor (TRSTT) tunnel probability Gate current modeling of tunneling real-space transfer transistor with negative differential resistance text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.