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Liu, Yubo 2015-07-22T22:45:19Z 2015-07-22T22:45:19Z 2017-07-23T09:15:31Z 2015-05 2015-04-17 The speed of wireline and wireless communication systems has been increasing aggressively over the past decade. Multi-GHz clocks are in demand more than ever. In particular, wireline inter-IC communications systems such as broadband Internet, multi-core CPU and system-on-chip have fueled the research on faster on-chip clock synthesizers. In addition, mobile products such as cell-phones and tablets have permeated the consumer market. Since these devices are battery-powered, it is necessary to minimize the battery consumption of the communication system circuitry inside to extend the battery life. As a result, low-power inter-IC communication design is another topic that is gaining interest. In high speed links, clocking circuitry is vital, and phase-locked loop (PLL) is at the heart of every on-chip clocking circuit. The clocking circuitry needs to be robust, low-power and fast in order to fulfill the increasing demand for high data rate links. The performance of the input/output (I/O) communication channel needs to scale proportionally with the semiconductor fabrication technology (SFT). However, conventional analog PLLs are often incompatible from one technology node to the next and require entirely new designs. In recent years, with the increased performance of digital circuits, all digital PLL (ADPLL) has achieved speed performance similar to that of analog PLL. Since digital logic is more robust, portable, and power efficient, ADPLL is gaining traction in research. This thesis presents the fundamentals and an in-depth analysis of the conventional analog PLL in Chapters 2 and 3. Then the discussion dives into ADPLL. Chapter 4 presents the building blocks and loop analysis of the ADPLL. Chapter 5 presents jitter sources and jitter analysis inside the ADPLL. Chapter 6 presents an ADPLL in model and transistor design. It has center frequency of 1.6GHz and operates from 1.2GHz to 2.0GHz. Chapter 7 concludes the thesis and discusses future work. Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2017-05-01 The student, Yubo Liu, accepted the attached license on 2015-04-15 at 11:45. The student, Yubo Liu, submitted this Thesis for approval on 2015-04-15 at 11:50. This Thesis was approved for publication on 2015-04-17 at 14:45. DSpace SAF Submission Ingestion Package generated from Vireo submission #7867 on 2015-07-22 at 14:24:42 Made available in DSpace on 2015-07-22T22:45:19Z (GMT). No. of bitstreams: 2 LIU-THESIS-2015.pdf: 1782565 bytes, checksum: 430b9a783a1b82352539eaa796883f66 (MD5) LICENSE.txt: 4205 bytes, checksum: e9d08fe5c0266f046716c5026509d770 (MD5) Previous issue date: 2015-04-17 Embargo set by: Seth Robbins for item 79977 Lift date: 2017-07-22T22:46:21Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Limited Restriction Lifted for Item 79977 on 2017-07-23T09:15:31Z. application/pdf http://hdl.handle.net/2142/78736 en Copyright 2015 Yubo Liu phase-locked loop (PLL) serial link all digital phase-locked loop (ADPLL) jitter Design of all digital phase-locked loop in serial link communication text text 2015-5 Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.