2026-09-21T09:38:14Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/80704 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Song, Bang-Sup Chen, Hsin-Shu 2015-09-25T20:07:43Z 2015-09-25T20:07:43Z 10000-01-01 2001 2001 This thesis presents a pipelined analog-to-digital converter (ADC) employing a capacitor error-averaging technique with look-ahead decision and digital error correction concepts that has been implemented in a CMOS technology to achieve high linearity and high speed. The capacitor error-averaging technique can perform an accurate multiply-by-two (x2) function required in high-resolution pipelined ADCs, while a high gain op-amp has been designed to minimize error due to finite DC gain. Three clock phases are required by the capacitor error-averaging technique (rather than the conventional two clock phases), and the look-ahead decision technique takes advantage of this by allowing the residue amplifiers a full clock phase of settling time (rather than a partial clock phase in a conventional pipelined ADC). The fully differential pipelined ADC achieves a throughput rate of 20 Msamples/s and a linearity of 14 b without any type of trimming or calibration. The prototype ADC, fabricated in a double-poly triple-metal 0.5-mum CMOS process, exhibits a differential nonlinearity (DNL) of +0.23/-0.28 least significant bit (LSB), an integral nonlinearity (INL) of +0.95/-1.06 LSB, a spurious-free dynamic range (SFDR) of 91.6 dB, and a signal-to-noise ratio (SNR) of 74.2 dB with a 1-MHz input and a 20-MHz clock. The chip occupies an active area of 10.8 mm 2 including digital logic, output buffers, and bond pads, and consumes 720 mW at 5 V. Made available in DSpace on 2015-09-25T20:07:43Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3017039.pdf: 4235287 bytes, checksum: d884bb50149923182951bd32abf0aa1e (MD5) Previous issue date: 2001 Embargo set by: Seth Robbins for item 81986 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 118 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2001. http://hdl.handle.net/2142/80704 (MiAaPQ)AAI3017039 eng Engineering, Electronics and Electrical High-Resolution Nyquist -Rate Analog -to -Digital Converter text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.