2026-09-19T18:58:40Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/80735 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Kang, Sung-Mo (Steve) Lee, Jaesik 2015-09-25T20:07:54Z 2015-09-25T20:07:54Z 10000-01-01 2001 2001 The design of on-chip ESD protection has become increasingly critical and difficult because of shrinking device feature sizes, high operating speed, and system-on-a-chip (SoC) environment. A complex ESD protection network can be easily exposed during normal operation and can cause the degradation of internal circuit performance. The ESD noise, defined as the loss introduced by ESD stress and protection network, can be caused by three mechanisms: I/O protection induced signal loss, mixed-signal coupling through power protection circuits, and latent damage. In this work, we have presented the characterization of the ESD noise. The effect of the ESD protection network on the noise performance of sensitive circuits is investigated with a test chip processed in a 0.18-mum CMOS technology. Experimental results demonstrate a critical relationship between ESD reliability and power/ground (PG) coupling: ESD robustness and PG coupling are conflicting design goals. We have presented a novel noise-aware design technique for superior noise margin and improved ESD reliability. The use of hierarchical electrostatic discharge (HED) provides a low impedance discharge path for any ESD event. The estimation of maximum PG voltage in digital circuits is critical to determine an optimal topology of protection circuits subject to noise constraints. Experimental results demonstrate the effectiveness of this method. Made available in DSpace on 2015-09-25T20:07:54Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3023113.pdf: 5026406 bytes, checksum: c1863311933b726e900aa717b3531271 (MD5) Previous issue date: 2001 Embargo set by: Seth Robbins for item 82017 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 105 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2001. http://hdl.handle.net/2142/80735 (MiAaPQ)AAI3023113 eng Engineering, Electronics and Electrical Design for ESD Reliability in High-Frequency Mixed-Signal Integrated Circuits text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.