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Kang, Sung-Mo (Steve) Jung, Seong-Ook 2015-09-25T20:08:02Z 2015-09-25T20:08:02Z 10000-01-01 2002 2002 Domino logic is known to consume more dynamic power than static logic. Low-voltage swing clock domino logic family is developed for substantial dynamic power saving. Delay-constrained power optimization algorithm allocates low supply voltage to logic gates such that dynamic power is minimized with timing constraint. Timing accuracy is ensured by accounting for timing variations due to gate-to-source voltage and input arrival time difference. Made available in DSpace on 2015-09-25T20:08:02Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3044130.pdf: 5265926 bytes, checksum: f6e302fa9701dc85539aa95956d81dfe (MD5) Previous issue date: 2002 Embargo set by: Seth Robbins for item 82046 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 125 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2002. http://hdl.handle.net/2142/80764 (MiAaPQ)AAI3044130 eng Engineering, Electronics and Electrical Low-Power High-Performance Dynamic Circuit Design for Ultra-Deep Submicron Technology text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.