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oai:www.ideals.illinois.edu:2142/80824 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Shanbhag, Naresh R. Mansour, Mohammad Monzer 2015-09-25T20:08:21Z 2015-09-25T20:08:21Z 10000-01-01 2003 2003 Decoder architectures for LDPC codes introduce another complexity dimension related to the on-chip interconnect bottleneck of LDPC decoders. A new parameterized-core-based design methodology targeted for scalable and programmable LDPC decoders is proposed. The methodology solves the problems of excessive memory overhead, high latency, and complex on-chip interconnect typical of existing decoder implementations, which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels. The methodology proposes: (1) The concept of architecture-aware LDPC code design that solves the interconnect bottleneck, (2) a faster and memory-efficient turbo-decoding algorithm for LDPC codes, and a reduced-complexity mechanism for message computations, (3) a programmable, scalable, and code-rate tunable architecture platform, and (4) a core-generator for high performance decoders. A decoder chip has been implemented using this methodology in 0.18 mum technology, which delivers a throughput of 1.6 Gbps at 125 MHz and consumes 760 mW of power. Made available in DSpace on 2015-09-25T20:08:21Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3086131.pdf: 11326146 bytes, checksum: 03dbebb321d80ea994dcba38d116b842 (MD5) Previous issue date: 2003 Embargo set by: Seth Robbins for item 82106 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 215 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2003. http://hdl.handle.net/2142/80824 (MiAaPQ)AAI3086131 eng Engineering, Electronics and Electrical VLSI Architectures for Iterative Channel Decoders text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.