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Shanbhag, Naresh R. Sridhara, Srinivasa Raghavan 2015-09-25T20:09:01Z 2015-09-25T20:09:01Z 10000-01-01 2006 2006 We mitigate the effects of intersymbol interference by employing a variable threshold inverter as an equalizer and operate the bus at rates beyond the rate governed by RC delay of the interconnect. We demonstrate even higher speeds by combining equalization with crosstalk avoidance coding. Simulation results for a 10-mm 32-bit bus in 0.13-mum CMOS technology show that 1.28x speed-up is achievable by equalization alone and 2.30x speed-up is achievable by joint equalization and coding. Made available in DSpace on 2015-09-25T20:09:01Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3223723.pdf: 2924297 bytes, checksum: 3aa2147783e285547539af110d19b0c8 (MD5) Previous issue date: 2006 Embargo set by: Seth Robbins for item 82246 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 102 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2006. http://hdl.handle.net/2142/80964 (MiAaPQ)AAI3223723 eng Engineering, Electronics and Electrical Communication-Inspired Design of on -Chip Buses text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.