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        <identifier>oai:www.ideals.illinois.edu:2142/80969</identifier>
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          <dc:contributor>Shanbhag, Naresh R.</dc:contributor>
          <dc:creator>Ahmed, Arshad</dc:creator>
          <dc:date>2015-09-25T20:09:02Z</dc:date>
          <dc:date>2015-09-25T20:09:02Z</dc:date>
          <dc:date>10000-01-01</dc:date>
          <dc:date>2006</dc:date>
          <dc:date>2006</dc:date>
          <dc:description>Finally, the applicability of soft-decoding for disk-drive applications is studied. Based on performance improvements and complexity requirements, generalized minimum distance decoding with maximum a priori soft-detection is selected, and the corresponding architecture is developed. The generalized minimum distance decoder is expected to give 0.5 dB gain over a hard-decoder at the target bit error-rate of 10-12 for the disk-drive channel. The architecture is synthesized using the Virtual Silicon standard cell library in a 0.13-mum CMOS process. It has an area of 7.29 mm&amp;sup2; and achieves a throughput of 8 Gbps.</dc:description>
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license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5)
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  Previous issue date: 2006</dc:description>
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Lift date: Forever
Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs</dc:description>
          <dc:description>Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs</dc:description>
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          <dc:identifier>(MiAaPQ)AAI3242776</dc:identifier>
          <dc:language>eng</dc:language>
          <dc:subject>Engineering, Electronics and Electrical</dc:subject>
          <dc:title>Algorithms and Architectures for Soft -Decoding Reed -Solomon Codes</dc:title>
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            <department>Electrical Engineering</department>
            <discipline>Electrical Engineering</discipline>
            <grantor>University of Illinois at Urbana-Champaign</grantor>
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            <name>Ph.D.</name>
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