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Ravishanker K. Iyer Nakka, Nithin Manikyam 2015-09-25T20:09:06Z 2015-09-25T20:09:06Z 10000-01-01 2006 2006 Our results show a decrease in overhead by 53% and a decrease in false positives by approximately 12% as compared to a duplication of all instructions. We detect all control logic errors that affect the instruction wakeup and scheduling mechanism. The combined hardware overhead due to the framework and modules is less than 10%. Our ongoing research is targeted towards implementing the framework and the modules on a Xilinx FPGA and towards refining the application analysis tools to detect key application characteristics, and then translating these characteristics into hardware modules that can be embedded into the framework. Made available in DSpace on 2015-09-25T20:09:06Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3242950.pdf: 5557400 bytes, checksum: 85e22477b22fc6bbb62865e0f788e048 (MD5) Previous issue date: 2006 Embargo set by: Seth Robbins for item 82264 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 227 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2006. http://hdl.handle.net/2142/80982 (MiAaPQ)AAI3242950 eng Engineering, Electronics and Electrical Reliability and Security Engine: A Processor-Level Framework for Application -Aware Detection and Recovery text Electrical and Computer Engineering Electrical and Computer Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.