2026-09-21T14:41:18Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/81213 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Song, Bang-Sup Kwak, Sung Ung 2015-09-25T20:10:05Z 2015-09-25T20:10:05Z 10000-01-01 1997 1997 This thesis presents a 5-5-5-6b pipelined ADC architecture that alleviates the requirements for initial capacitor matching and residue amplifier settling accuracy. The two 5-bit MSB stages are digitally calibrated to implement a 15-bit, 5 Msample/s low-spurious ADC using 1.4 $\mu$m CMOS. A skip-and-fill algorithm with non-linear interpolation also opens up the possibility of calibrating ADCs in the background synchronously with their normal operations. Interpolation results for the background calibration are compared with the foreground calibration results. The prototype ADC exhibits a DNL of +0.75/$-$0.6 LSB, an INL of +1.77/$-$1.58 LSB, and all spurious components are suppressed to below $-$93 dB when sampled at 5 MHz. The chip occupies an active area of 27 mm$\sp2,$ and the analog part consumes 60 mW at 5 V. Memory and arithmetic units for calibration are supplied externally in testing. Made available in DSpace on 2015-09-25T20:10:05Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9812665.pdf: 4929976 bytes, checksum: 9bbee6af91dd3557670a2248b27f0763 (MD5) Previous issue date: 1997 Embargo set by: Seth Robbins for item 82494 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 139 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997. http://hdl.handle.net/2142/81213 (MiAaPQ)AAI9812665 eng Engineering, Electronics and Electrical Low-Spurious Analog-to-Digital Conversion Using Multi-Stage Code-Error Calibration text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.