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oai:www.ideals.illinois.edu:2142/81229 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Rosenbaum, Elyse Raha, Prasun Kumar 2015-09-25T20:10:09Z 2015-09-25T20:10:09Z 10000-01-01 1998 1998 For the first time, a circuit level simulation tool for CMOS-on-SOI ESD protection networks is presented. The simulator, SOI-iETSIM, has built-in device models for completely coupled electrothermal simulation of SOI protection devices operating in the high current regime. The implementation of thermal models in a circuit level simulator for SOI circuits is discussed. Modeling the floating body effects in SOI MOSFETs and their effect on the device operation in the snapback mode is also discussed. The implementation of the parasitic BJT in the SOI MOSFET model is different from previously published models. Device simulation examples and an SOI-ESD protection circuit simulation example are also presented. Made available in DSpace on 2015-09-25T20:10:09Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9834733.pdf: 3154176 bytes, checksum: a6b03edf8a64947ed2ac667e50353ff4 (MD5) Previous issue date: 1998 Embargo set by: Seth Robbins for item 82510 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 107 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998. http://hdl.handle.net/2142/81229 (MiAaPQ)AAI9834733 eng Engineering, Electronics and Electrical Modeling, Simulation and Design of EOS/ESD Protection Devices and Circuits in Silicon-on-Insulator Technology text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.