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Farid N. Najm Nemani, Mahadevamurty 2015-09-25T20:10:15Z 2015-09-25T20:10:15Z 10000-01-01 1998 1998 High-level power estimation requires high-level predictions of circuit average activity, area, and delay, in order to estimate power. The main contribution of this research is development of predictors (estimators) for activity, area, and delay for combinational circuits, thus making it possible to estimate power at the RT level. All of the above predictors work with a functional description of the design and avoid the time consuming translation of the RT description into a circuit-level description, thus making them fast, which in turn enables the designer to explore the area, delay, and power space early in the design. Made available in DSpace on 2015-09-25T20:10:15Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9904547.pdf: 6857464 bytes, checksum: 565e30e5930624c3e423ccc0407163c2 (MD5) Previous issue date: 1998 Embargo set by: Seth Robbins for item 82531 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 146 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998. http://hdl.handle.net/2142/81250 (MiAaPQ)AAI9904547 eng Engineering, Electronics and Electrical High-Level Power Estimation text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.