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oai:www.ideals.illinois.edu:2142/81278 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Ibrahim Hajj Bellas, Nikolaos 2015-09-25T20:10:22Z 2015-09-25T20:10:22Z 10000-01-01 1999 1999 More specifically, we propose a technique that uses an additional mini cache located between the instruction cache (I-Cache) and the CPU core; the mini cache buffers instructions that are nested within loops and are continuously fetched from the I-Cache. This mechanism can create very substantial energy savings, since the I-Cache unit is one of the main power consumers in most of today's high-performance microprocessors. Results are reported for the SPEC95 benchmarks in the R-4400 processor which implements the MIPS2 instruction set architecture. Made available in DSpace on 2015-09-25T20:10:22Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9921661.pdf: 5766993 bytes, checksum: f01776a091deb8b2ec3d622e524bf853 (MD5) Previous issue date: 1999 Embargo set by: Seth Robbins for item 82559 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 114 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999. http://hdl.handle.net/2142/81278 (MiAaPQ)AAI9921661 eng Energy Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.