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oai:www.ideals.illinois.edu:2142/81301 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Kang, Sung-Mo (Steve) Yuan, Li-Pen 2015-09-25T20:10:27Z 2015-09-25T20:10:27Z 10000-01-01 1999 1999 The bottleneck of voltage drop analysis lies in the matrix inversion that is involved in solving the circuit equations of the power/ground bus. To remove the bottleneck, we proposed an algorithm to quickly estimate the cycle-by-cycle maximum voltage drop values of a circuit driven by an input sequence. Based on the rank of the estimates, a small set of input vectors is selected for detailed analysis to identify the worst-case voltage drop behavior. The pruning strategy has been applied to a set of industry designs and is found to be on average three times faster than direct network analysis. Compared to a straightforward approach of using the total power as the estimator, the proposed algorithm demonstrates higher run-time efficiency and better consistency with the actual simulation results. Made available in DSpace on 2015-09-25T20:10:27Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9945039.pdf: 5858628 bytes, checksum: e9d1670819ffea584bbb0f8d32e2eaec (MD5) Previous issue date: 1999 Embargo set by: Seth Robbins for item 82582 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 140 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999. http://hdl.handle.net/2142/81301 (MiAaPQ)AAI9945039 eng Engineering, Electronics and Electrical Power and Voltage Drop Analyses in VLSI Circuits text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.